Digital Logic Design

Topics

The full DLD unit map, preserved as its own destination page so the course hub can stay clean and consistent.

UNIT_MAP
01 // Course Content

Unit Breakdown

From Boolean algebra to finite state machines, these are the core checkpoints for the course.

UNIT_01Active

Boolean Algebra & Logic

Boolean identities, De Morgan's theorem, truth tables, canonical forms, and the symbolic groundwork for later circuit design.

Truth TablesSOP/POSLogic Laws
UNIT_02Active

Logic Gates & Circuits

Gate families, equivalence, gate-level composition, and the translation between algebraic expressions and actual circuit structures.

AND/OR/NOTNAND/NORGate Equivalence
UNIT_03In Progress

Combinational Logic

Adders, subtractors, multiplexers, decoders, encoders, and the design habits behind reusable combinational modules.

AddersMUX/DEMUXDecoders
UNIT_04In Progress

Karnaugh Maps

Map-based minimization for SOP and POS forms, prime implicants, essential groups, and don't-care handling.

2-4 VariablesPrime ImplicantsOptimization
UNIT_05Upcoming

Sequential Logic

Latches, flip-flops, timing behavior, counters, and the shift from stateless logic into memory-driven systems.

Flip-FlopsCountersTiming
UNIT_06Upcoming

Finite State Machines

Moore and Mealy models, state minimization, transition diagrams, and structured sequential design.

MooreMealyState Diagrams